1. Field of the Invention
The present invention generally relates to integrated circuit manufacturing and, more particularly, to the use of flowable oxide (FOX) layers as insulators or barriers for semiconductor devices and the protection of FOX layers from degradation in such applications.
2. Description of the Prior Art
Increases in both performance and manufacturing economy with increased integration density have led to the use of design rules with extremely small feature sizes and closeness of spacing in integrated circuit design. Reduced interconnection length between devices included in integrated circuits generally reduces signal propagation time and increases noise immunity. However, as integrated circuits are scaled to smaller design rules, reductions in wiring delays are diminished by increases in resistance (due to decreased cross-sectional area) and capacitance (due to increased connection proximity). This effect can only be ameliorated by reduced resistivity of conductors and/or dielectric constant of insulators. Accordingly, advanced dielectric materials having low dielectric constants have been developed and are used in manufacture of integrated circuits.
Flowable oxides (FOXs) are one family of low dielectric constant materials developed for use in the manufacture of integrated circuits. FOX insulators have good gapfill properties. These materials form a structure in which bridging oxygen atoms are shared between molecules. While the dielectric constant is low, the bridging oxygen atoms are strained and can be attacked by numerous chemicals or result in rapidly propagating cracks from relatively minor physical damage. For that reason, unprotected FOX materials are not generally considered suitable for formation of layers even though they exhibit good planarizing characteristics that would support high resolution lithographic processes.
Damascene processing is a well-understood and mature technology which is particularly useful for mechanically forming robust connections of superior electrical integrity at very small sizes and close spacings. Basically, a Damascene process defines the desired shape of conductors by the formation of a groove or recess in the surface of a dielectric material followed by deposition of a layer of metal of sufficient thickness to fill the recesses. The layer of metal is then readily patterned by planarization to the original surface of the dielectric by any known process such as polishing. The structure so formed fully supports the metal at the bottom and sides of a connection (which may be made of soft materials such as gold, aluminum or copper or other materials such as tungsten) and thus is resistant to metal migration, damage or the like. The groove or recess can also generally be formed with greater precision and regularity of the edges of the pattern than can be achieved by direct patterning of a layer of metal.
When forming damascene conductors on a dielectric layer above a substantially completed chip, however, two patterning processes are required for formation of the interconnect patterns and for forming connections to devices on the chip in the form of vias, respectively. These two patterning processes followed by metal deposition and planarization are collectively referred to as a dual Damascene process.
However, most FOX materials are readily attacked by most lithographic resist developers which are generally of high pH. Moreover, when the FOX material is attacked by resist developers, the amount of material which may be removed is not readily controllable and may undercut the resist pattern. Thus, when the FOX is etched, even with a well-controlled etchant, the resulting via shape may be quite distorted and vias will lack uniformity across the chip and possibly be irregularly and unreliably registered with the structures on the chip to which the vias are to form connections. Moisture is similarly damaging to FOX materials.
Therefore, the surface of a FOX material needs to be protected with a further layer of material. One approach to the protection of a FOX layer in a semiconductor is the TaN/Ta system. However, TaN barriers may have very small pinholes exposing the FOX to a metallic conductor, typically copper. Such systems are known as extrudable systems because the metallic conductor, when heated or otherwise under pressure, will seek to extrude into surrounding materials. Unfortunately, this exposure causes other reliability problems associated with the extrusion of the metallic conductor into the FOX or corrosion of the metallic conductor or both. For example, when the conductive paths in an integrated circuit chip are at close pitch, even a very small amount of copper extrusion through a pinhole defect can cause a short circuit between one copper interconnect line and a second copper interconnect line. Furthermore, some materials that may be otherwise desirable for metallization layers will not adhere to FOX materials. U.S. Pat. No. 5,530,293, issued to Cohen et al. on Jun. 25, 1996 (Cohen), describes a method of capping FOX material with 1000 .ANG. of SiO.sub.2 by plasma enhanced chemical vapor deposition (PECVD) or low plasma chemical vapor deposition (LPCVD) to increase adhesion.
Protection of the surface of the FOX material with a further layer of material such as another dielectric is not practical in some semiconductor structures such as formation of connection vias in a dual Damascene process. Virtually any otherwise suitable material for protection of a FOX material would have a dielectric constant which is higher than that of the FOX and even a very thin layer would increase capacitance at a location where capacitance may be critical and may possibly require a different etchant and/or an additional etching process to remove in accordance with a resist pattern. Additionally, while a protective layer may be deposited on an original surface of a FOX layer, deposition of a protective layer in an etched feature (e.g. in a trench or groove) would require additional process steps as well as compromising the low capacitance of any conductive structure formed therein for which the FOX material was employed.
The basic concept of using a resist is predicated on the assumption that the underlying material will not be affected by the processing and development of the resist until the resist pattern is fully formed. Since the FOX material removal by the resist developer appears to be a function of the breaking of fragile shared oxygen bonds, it is unlikely that a developer could be found which would not attack the FOX material. Accordingly, at the present state of the art, processes using multiple resist layers would provide no significant benefit toward reduction of the problem.
It is known to protect a FOX with a higher quality oxide. However known methods generally focus on the use of a separate oxide film to accomplish this objective. Furthermore, U.S. Pat. No. 5,085,893, issued to Keith D. Weiss et al. on Feb. 4, 1992 for a "PROCESS FOR FORMING A COATING ON A SUBSTRATE USING A SILSESQUIOXANE RESIN", teaches that a FOX can be converted to a high quality ceramic through oxidizing the FOX. However, the dielectric constant of the volume of FOX material converted to oxide is increased which increases the capacitance. Similarly, the provision of a separate protective layer of another material would significantly alter the average dielectric constant and potentially introduce adhesion problems. Thus, there is a need for a very thin protective barrier which cannot be formed by previously known methods.
In summary, use of a FOX material to underlie or support interconnection metallization allows the use of damascene processes to produce conductors and vias only with the likelihood that manufacturing yield will be compromised. While FOX materials can be used as a gap fill material over connections applied to a surface the advantages of damascene connections noted above are not achieved thereby. No technique has been available for avoiding the basic incompatibility of FOX materials and resist developers in processes requiring a sequence of patterned etch steps, such as in a dual damascene process, particularly for accommodating fine pitch design rules for high density integrated circuits where the low dielectric constant of FOX materials is particularly critical.